I worked for AWS Security and earned my PhD in Electrical and Computer Engineering from Virginia Tech. I started my academic journey with a Bachelor's in Electrical and Electronic Engineering from BUET, then completed a Master's at Auburn University. My work focuses on hardware and embedded systems security—both finding vulnerabilities and building defenses. During my PhD, I was part of the FoRTE Research Group led by Dr. Matthew Hicks, where I worked on three main research areas:
Hardware-Oriented System Security: My interest in system-level security from a hardware perspective centers on how physical and electrical phenomena—such as device aging, process variation, timing behavior, and power consumption—can lead to system vulnerabilities or be harnessed to design security primitives using non-deterministic properties.
Cloud FPGA Security: Cloud service providers, such as AWS, offer CPU-FPGA virtual machines to accelerate compute-intensive workloads. However, the direct device-level access provided by FPGAs introduces numerous security implications. For instance, FPGAs can potentially act as power sensors for an entire server rack. I examine how an RTL-level access can significantly expands the attack surface in CPU-FPGA cloud environments.
Fake Chip Detection and Anti-Counterfeit Framework Design: The issue of counterfeit chips has become a severe problem, worsened by the ongoing global chip shortage due to factors such as the pandemic, geopolitical tensions, and natural disasters. To tackle this problem, I develop robust schemes to detect and prevent counterfeit chips, aiming to enhance transparency and protect the integrity of the supply chain.
This project shows how long-term-data remanence is a threat to Trusted Execution System such as ARM TrustZone.
Creating artificial data retention in on-chip SRAM cell. This is a cold-style attack on on-chip SRAM, but without any cooling effect needed
This project is designed to conceal information in the analog layer of static random access memories (SRAM) with plausible deniability. The idea is to burn data into the transistor so that it is reflected in the SRAM's power-on state. The hidden information coexists with the data in the digital layer. That is, the system shows no signs of hidden data anywhere.
Cloud service providers typically restrict access to low-level device information, such as device DNA. This project introduces an RTL design that utilizes the FPGA clock synthesizer to extract device behavior, enabling identification of specific FPGAs in the cloud. The system includes a hardware/software suite for seamless integration with AWS F1 instances, featuring necessary RTL and system service modules for signature extraction during the boot phase of the host CPU.